build started at Fri Mar 13 14:18:43 EDT 2026 port directory: /usr/ports/cad/yosys-systemverilog package name: yosys-systemverilog-2023.06.14_1 building for: FreeBSD pkg.DaveG.ca 14.4-RELEASE FreeBSD 14.4-RELEASE 1404000 amd64 maintained by: yuri@FreeBSD.org Makefile datestamp: -rw-r--r-- 1 root wheel 3518 Oct 28 16:11 /usr/ports/cad/yosys-systemverilog/Makefile Ports top last git commit: 26b198eb3ee3 Ports top unclean checkout: no Port dir last git commit: 6ecfc25ff4e0 Port dir unclean checkout: no Poudriere version: poudriere-git-3.4.2 Host OSVERSION: 1500068 Jail OSVERSION: 1404000 Job Id: ---Begin Environment--- SHELL=/bin/sh OSVERSION=1404000 UNAME_v=FreeBSD 14.4-RELEASE 1404000 UNAME_r=14.4-RELEASE BLOCKSIZE=K MAIL=/var/mail/root MM_CHARSET=UTF-8 LANG=C.UTF-8 NBPARALLEL=14 STATUS=1 HOME=/root PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin MAKE_OBJDIR_CHECK_WRITABLE=0 USER=root POUDRIERE_NAME=poudriere-git LIBEXECPREFIX=/usr/local/libexec/poudriere POUDRIERE_VERSION=3.4.2 MASTERMNT=/usr/local/poudriere/data/.m/freebsd_14_4_x64-HEAD-ALL/ref LC_COLLATE=C POUDRIERE_BUILD_TYPE=bulk PACKAGE_BUILDING=yes SAVED_TERM=tmux-256color PWD=/usr/local/poudriere/data/.m/freebsd_14_4_x64-HEAD-ALL/ref/.p P_PORTS_FEATURES=FLAVORS SUBPACKAGES SELECTED_OPTIONS MASTERNAME=freebsd_14_4_x64-HEAD-ALL PARALLEL_PIDS=53300 53302 53305 53310 53311 53316 53321 53331 53342 53350 53361 53365 53378 SCRIPTPREFIX=/usr/local/share/poudriere SCRIPTNAME=bulk.sh OLDPWD=/tmp POUDRIERE_PKGNAME=poudriere-git-3.4.2 SCRIPTPATH=/usr/local/share/poudriere/bulk.sh POUDRIEREPATH=/usr/local/bin/poudriere ---End Environment--- ---Begin Poudriere Port Flags/Env--- PORT_FLAGS= PKGENV= FLAVOR= MAKE_ARGS= ---End Poudriere Port Flags/Env--- ---Begin OPTIONS List--- ===> The following configuration options are available for yosys-systemverilog-2023.06.14_1: TCMALLOC=on: Use the tcmalloc memory allocation library ===> Use 'make config' to modify these settings ---End OPTIONS List--- --MAINTAINER-- yuri@FreeBSD.org --End MAINTAINER-- --CONFIGURE_ARGS-- --End CONFIGURE_ARGS-- --CONFIGURE_ENV-- MAKE=/usr/local/bin/gmake PKG_CONFIG=pkgconf PYTHON="/usr/local/bin/python3.11" XDG_DATA_HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work XDG_CACHE_HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/.cache HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work TMPDIR="/tmp" PATH=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig SHELL=/bin/sh CONFIG_SHELL=/bin/sh --End CONFIGURE_ENV-- --MAKE_ENV-- DESTDIR= HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/yosys-systemverilog-49069fb-2023-06-14 XDG_DATA_HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work XDG_CONFIG_HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work XDG_CACHE_HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/.cache HOME=/wrkdirs/usr/ports/cad/yosys-systemverilog/work TMPDIR="/tmp" PATH=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/.bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/root/bin PKG_CONFIG_LIBDIR=/wrkdirs/usr/ports/cad/yosys-systemverilog/work/.pkgconfig:/usr/local/libdata/pkgconfig:/usr/local/share/pkgconfig:/usr/libdata/pkgconfig MK_DEBUG_FILES=no MK_KERNEL_SYMBOLS=no SHELL=/bin/sh NO_LINT=YES PREFIX=/usr/local LOCALBASE=/usr/local CC="cc" CFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " CPP="cpp" CPPFLAGS="-I/usr/local/include" LDFLAGS=" `pkg-config --libs libtcmalloc` -L/usr/local/lib " LIBS="" CXX="c++" CXXFLAGS="-O2 -pipe -fstack-protector-strong -fno-strict-aliasing " BSD_INSTALL_PROGRAM="install -s -m 555" BSD_INSTALL_LIB="install -s -m 0644" BSD_INSTALL_SCRIPT="install -m 555" BSD_INSTALL_DATA="install -m 0644" BSD_INSTALL_MAN="install -m 444" --End MAKE_ENV-- --PLIST_SUB-- PYTHON_INCLUDEDIR=include/python3.11 PYTHON_LIBDIR=lib/python3.11 PYTHON_PLATFORM=freebsd14 PYTHON_SITELIBDIR=lib/python3.11/site-packages PYTHON_SUFFIX=311 PYTHON_BASESUFFIX=311 PYTHON_TAG=.cpython-311 PYTHON_SOABI=.cpython-311 PYTHON_VER=3.11 PYTHON_BASEVER=3.11 PYTHON_VERSION=python3.11 PYTHON2="@comment " PYTHON3="" OSREL=14.4 PREFIX=%D LOCALBASE=/usr/local RESETPREFIX=/usr/local LIB32DIR=lib DOCSDIR="share/doc/yosys-systemverilog" EXAMPLESDIR="share/examples/yosys-systemverilog" DATADIR="share/yosys-systemverilog" WWWDIR="www/yosys-systemverilog" ETCDIR="etc/yosys-systemverilog" --End PLIST_SUB-- --SUB_LIST-- PYTHON_INCLUDEDIR=/usr/local/include/python3.11 PYTHON_LIBDIR=/usr/local/lib/python3.11 PYTHON_PLATFORM=freebsd14 PYTHON_SITELIBDIR=/usr/local/lib/python3.11/site-packages PYTHON_SUFFIX=311 PYTHON_BASESUFFIX=311 PYTHON_TAG=.cpython-311 PYTHON_SOABI=.cpython-311 PYTHON_VER=3.11 PYTHON_BASEVER=3.11 PYTHON_VERSION=python3.11 PYTHON2="@comment " PYTHON3="" PREFIX=/usr/local LOCALBASE=/usr/local DATADIR=/usr/local/share/yosys-systemverilog DOCSDIR=/usr/local/share/doc/yosys-systemverilog EXAMPLESDIR=/usr/local/share/examples/yosys-systemverilog WWWDIR=/usr/local/www/yosys-systemverilog ETCDIR=/usr/local/etc/yosys-systemverilog --End SUB_LIST-- ---Begin make.conf--- DEFAULT_VERSIONS+=pgsql=15 DEFAULT_VERSIONS+=php=82 DISABLE_LICENSES=yes SELECTED_OPTIONS+=OPENBLAS ARCHDEF=AMD64K10h64SSE3 USE_PACKAGE_DEPENDS=yes BATCH=yes WRKDIRPREFIX=/wrkdirs PORTSDIR=/usr/ports PACKAGES=/packages DISTDIR=/distfiles FORCE_PACKAGE=yes PACKAGE_BUILDING=yes PACKAGE_BUILDING_FLAVORS=yes #### #### DEFAULT_VERSIONS+=pgsql=15 DEFAULT_VERSIONS+=php=82 DISABLE_LICENSES=yes SELECTED_OPTIONS+=OPENBLAS ARCHDEF=AMD64K10h64SSE3 WITH_CCACHE_BUILD=yes CCACHE_DIR=/root/.ccache #### Misc Poudriere #### .include "/etc/make.conf.ports_env" GID=0 UID=0 ---End make.conf--- --Resource limits-- cpu time (seconds, -t) unlimited file size (512-blocks, -f) unlimited data seg size (kbytes, -d) 33554432 stack size (kbytes, -s) 524288 core file size (512-blocks, -c) unlimited max memory size (kbytes, -m) unlimited locked memory (kbytes, -l) unlimited max user processes (-u) 89999 open files (-n) 3769812 virtual mem size (kbytes, -v) unlimited swap limit (kbytes, -w) unlimited socket buffer size (bytes, -b) unlimited pseudo-terminals (-p) unlimited kqueues (-k) unlimited umtx shared locks (-o) unlimited pipebuf (-y) unlimited --End resource limits-- =================================================== Ignoring: is marked as broken: incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845 =========================================================================== build of cad/yosys-systemverilog | yosys-systemverilog-2023.06.14_1 ended at Fri Mar 13 14:18:44 EDT 2026